Reductions in size of metal-oxide-semiconductor field-effect transistors (MOSFET), including reductions in gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. To further enhance transistor performance, strain may be introduced in the transistor channel for improving carrier mobilities. Generally, it is desirable to induce a tensile strain in the n-channel of an nMOSFET in the source-to-drain direction, and to induce a compressive strain in the p-channel of a pMOSFET in the source-to-drain direction. There are several existing approaches of introducing strain in the transistor channel region.
In one approach, strain in the channel is introduced after the transistor is formed. In this approach, a high stress film is formed over a completed transistor structure formed in a silicon substrate. The high stress film or stressor exerts significant influence on the channel, modifying the silicon lattice spacing in the channel region, and thus introducing strain in the channel region. In this case, the stressor is placed above the completed transistor structure. This scheme is described, for example, in a paper by A. Shimizu et al., entitled “Local mechanical stress control (LMC): a new technique for CMOS performance enhancement,” published in pp. 433-436 of the Digest of Technical Papers of the 2001 International Electron Device Meeting. This approach has met with limited success, however, since the formation of the stressed dielectric layer of a particular type of stress e.g., tensile or compressive, has a degrading electrical performance effect on a complementary field-effect transistor that includes an n-channel field-effect transistor and a p-channel field-effect transistor, which operate with opposite types of majority charge carriers. For example, as an nMOSFET device performance is improved by a particular stress, pMOSFET device performance is degraded.
As shown in U.S. Appl. Ser. No. 2003/0040158, a first nitride layer providing tensile stress is formed to cover the nMOSFET device in a complementary field-effect transistor and a second nitride layer providing compressive stress is formed to cover the pMOSFET device of the complementary field-effect transistor. The tensile stress of the first nitride layer is applied to the corresponding surface area of the substrate, thereby decreasing the compressive stress existing in the channel region of the n-channel MOSFET. Thus, the electron mobility is increased and as a result, the current driving capability of the n-channel MOSFET is improved. Likewise, the compressive stress of the second nitride layer is applied to the corresponding surface area of the substrate, thereby decreasing the tensile stress existing in the channel region of the p-channel MOSFET.
Despite the use of nitride layers to enhance the stress arising in the channel regions of MOSFET devices, carrier mobility and overall device performance would be enhanced still further if additional stress could be provided.